Process of manufacturing semiconductor device

ABSTRACT

A process of manufacturing a semiconductor device having a dual gate CMOS transistor in which an nMOS transistor in the dual gate CMOS transistor is formed by the steps of: (a) forming a gate insulating film and a silicon film on a semiconductor substrate; (b) implanting n-type impurities into the silicon film in an nMOS region of the semiconductor substrate; (c) forming a conductive film on the silicon film; and (d) patterning the silicon film and the conductive film into a gate electrode.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application is related to Japanese application No.2000-148053 filed on May 19, 2000, whose priority is claimed under 35USC §119, the disclosure of which is incorporated by reference in itsentirety.

BACKGROUND OF THE INVENTION

[0002] 2. Field of the Invention

[0003] The present invention relates to a process of manufacturing asemiconductor device. In particular, it relates to a process ofmanufacturing a semiconductor device having a miniaturized dual gateCMOS transistor.

[0004] 2. Description of Related Art

[0005] In a trend to miniaturization of MOS transistors due todevelopment of semiconductor processing techniques, a dual gate CMOStransistor has generally been applied since it inhibits short channeleffect and reduces OFF current. The dual gate CMOS transistor utilizesan n-type polysilicon file and a p-type polysilicon film as gateelectrodes of an nMOS transistor and a pMOS transistor, respectively.

[0006] In the dual gate CMOS transistor, the gate electrode is implantedwith n- or p-type impurities by ion implantation for forming a shallowjunction as a source/drain region. Accordingly, the impurities are notsufficiently introduced into the neighborhood of a gate insulating filmand depletion occurs in the gate electrode, which deterioratestransistor properties.

[0007] Further, in the formation of the pMOS transistor, BF₂ ions aregenerally implanted to form a source/drain region of a shallow junction.Boron ions introduced into the gate electrode tends to cause enhanceddiffusion in the gate insulating film due to the presence of fluorineand penetrates the gate insulating film to diffuse into a channelregion, which varies a threshold value of the transistor. The currentMOS transistor utilizes a gate insulating film which is as very thin asseveral tens of Å and it tends to be further thinned due to theminiaturization of the MOS transistor. Therefore it is considered thatthe penetration of boron ions through the gate insulating film willoccur more remarkably.

[0008] Japanese Unexamined Patent Publication No. HEI 6(1994)-310666 hasproposed a method of preventing the depletion of the gate electrode asdescribed below.

[0009] As shown in FIG. 3(a), a p-well 52 a and an n-well 52 b areformed in a nMOS region and an pMOS region, respectively by ionimplantation in a semiconductor substrate 50 provided with deviceisolation films 51.

[0010] Then, a gate insulating film 53 and a silicon film 54 are formedon the semiconductor substrate 50 as shown in FIG. 3(b) and n- andp-type impurities are implanted to the nMOS region and the pMOS region,respectively. The obtained semiconductor substrate is then annealed toform an n-type polysilicon film 54 a and a p-type polysilicon film 54 bas shown in FIG. 3(c).

[0011] Further, the n-type polysilicon film 54 a and the p-typepolysilicon film 54 b are patterned into a desired configuration to formgate electrodes as shown in FIG. 3(d). Ion implantation is thenperformed to form LDD regions 56 a and 56 b in the nMOS region and thepMOS region, respectively. Then an insulating film is deposited on theentire surface of the semiconductor substrate 50 and etched back to formsidewall spacers 55 onto the gate electrodes.

[0012] With the sidewall spacers 55 and the gate electrodes as a mask,ion implantation is carried out to the nMOS region and the pMOS region,respectively, and annealing is performed to form source/drain regions 57a and 57 b as shown in FIG. 3(e).

[0013] Thereafter, a titanium film is formed on the resultingsemiconductor substrate 50 and thermally treated to provide a titaniumsilicide film 58 on the source/drain regions 57 a and 57 b and the gateelectrodes. An interlayer insulating film 59 and contact holes areprovided and then contact plugs 60 and a wiring layer 61 are formed by awiring process.

[0014] In summary, a resist mask is formed in advance byphotolithography before the formation of the gate electrode, with whichsuitable ions are implanted to the polysilicon films in the nMOS regionand the pMOS region, respectively, and then annealed to obtain the nMOStransistor and the pMOS transistor.

[0015] Through these steps, impurities are sufficiently introduced intothe gate electrodes in the neighborhood of the gate insulating film andthe depletion of the gate electrodes is prevented.

[0016] In the above-mentioned method, however, an additionalphotolithography step has to be carried out for ion implantation to thegate electrodes. Further, annealing has to be carried out for arelatively long period or in plural times in order to diffuse theimpurities from the surface of the gate electrode to an interfacebetween the gate electrode and the gate insulating film. Accordingly,manufacturing steps are increased and lengthened, which leads to anincrease of production costs.

[0017] The depletion of the gate electrode can be prevented by thinningthe polysilicon film consisting the gate electrode or increasing a doseand an acceleration energy for ion implantation for forming thesource/drain region. However, the former may increase the amount ofboron ions penetrating the gate insulating film or deteriorate the gateinsulating film due to stress applied by a salicide step. The latter maylead short channel effect and increase junction leak current caused bydefects of the semiconductor substrate due to ion implantation as wellas promote the penetration of boron ions through the gate insulatingfilm particularly in the pMOS transistor.

[0018] Further, Japanese Unexamined Patent Publication No. HEI11(1999)-307765 has proposed a method of avoiding multiplication of thephotolithography steps. According to this method, a polysilicon film oflarge particle diameter doped with phosphorus is formed on the entiresurface of a semiconductor substrate and a non-doped polysilicon film isformed thereon. These polysilicon films are patterned to form gateelectrodes. Thereafter, at the ion implantation for forming asource/drain region, phosphorus previously doped as n-type impuritiesare compensated by p-type impurities of high concentration to provide ap-type gate electrode in the pMOS region.

[0019] However, when the p-type impurities are implanted in a dosecapable of preventing the depletion of the gate electrode, inhibition ofshort channel effect becomes insufficient as this method involveseliminating the n-type impurities and giving p-type conductivity to thegate electrode by the ion implantation for forming the source/drainregion.

[0020] This method may prevent the depletion of the gate electrode byannealing at high temperature and/or for a long time to activate theimpurities. However, the method is still problematic in that theimpurity diffusion in the source/drain region is enhanced, and shortchannel effect and penetration of boron ions through the gate insulatingfilm in the pMOS transistor remarkably occur.

[0021] The penetration of boron ions through the gate insulating filmcan be inhibited by performing the ion implantation for forming thesource/drain region with boron ions free from fluorine. However, the useof boron ions makes the formation of a shallow source/drain regiondifficult, so that short channel effect cannot be prevented and OFFcurrent increases.

[0022] It may be possible to inhibit the penetration of boron ions byusing amorphous silicon as a gate electrode material instead ofpolysilicon, utilizing polysilicon of large particle diameter asproposed in Japanese Unexamined Patent Publication No. HEI11(1999)-297852, or providing an extremely thin insulating film at aninterface within a multilayered silicon film. However, impuritydiffusion in the gate electrode is hindered and therefore the depletionof the gate electrode easily occurs.

[0023] Thus, in the present situation, there has not been establishedyet a method which allows all the requirements for prevention of shortchannel effect, reduction of OFF current, inhibition of depletion of thegate electrode and prevention of penetration of boron ions through thegate insulating film in a miniaturized dual gate CMOS transistor.

SUMMARY OF THE INVENTION

[0024] The present invention has been achieved in view of theabove-mentioned problems. An objective of the present invention is toprovide a process of manufacturing a semiconductor device including aminiaturized dual gate CMOS transistor of high performance and highreliability, the method being capable of preventing the short channeleffect, reducing the OFF current, inhibiting the depletion of the gateelectrode and preventing the penetration of boron ions through the gateinsulating film, without multiplying and lengthening the manufacturingsteps.

[0025] According to the present invention, provided is a process ofmanufacturing a semiconductor device having a dual gate CMOS transistorin which an nMOS transistor in the dual gate CMOS transistor is formedby the steps of: (a) forming a gate insulating film and a silicon filmon a semiconductor substrate; (b) implanting n-type impurities into thesilicon film in an nMOS region of the semiconductor substrate; (c)forming a conductive film on the silicon film; and (d) patterning thesilicon film and the conductive film into a gate electrode.

[0026] Further, the present invention provides a process ofmanufacturing a semiconductor device having a dual gate CMOS transistorcomprising the steps of: (a) forming a gate insulating film and asilicon film on a semiconductor substrate; (b′) implanting n-typeimpurities into the silicon film in an nMOS region and p-type impuritiesinto the silicon film in an pMOS region of the semiconductor substrate;(c) forming a conductive film on the silicon film; and (d′) patterningthe silicon film and the conductive film into gate electrodes for thenMOS and pMOS transistor.

[0027] These and other objects of the present application will becomemore readily apparent from the detailed description given hereinafter.However, it should be understood that the detailed description andspecific examples, while indicating preferred embodiments of theinvention, are given by way of illustration only, since various changesand modifications within the spirit and scope of the invention willbecome apparent to those skilled in the art from this detaileddescription.

BRIEF DESCRIPTION OF THE DRAWINGS

[0028] FIGS. 1(a) to 1(i) are schematic sectional views of a major partfor illustrating an embodiment of a process of manufacturing asemiconductor device according to the present invention;

[0029] FIGS. 2(a) to 2(i) are schematic sectional views of a major partfor illustrating another embodiment of a process of manufacturing asemiconductor device according to the present invention; and

[0030] FIGS. 3(a) to 3(f) are schematic sectional views of a major partfor illustrating a process of manufacturing a semiconductor deviceaccording to the prior art.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0031] The present invention relates to a process of manufacturing adual gate CMOS transistor. Mainly the process, for forming an nMOStransistor in the dual gate CMOS transistor, includes the steps of: (a)forming a gate insulating film and a silicon film on a semiconductorsubstrate; (b) implanting n-type impurities in the silicon film in annMOS region of the semiconductor substrate; (c) forming a conductivefilm on the silicon film; and (d) patterning the silicon film and theconductive film into a gate electrode.

[0032] As the semiconductor substrate used in the process of the presentinvention, various kinds of substrate can be applied, for example,element semiconductor substrates such as of silicon, germanium and thelike, compound semiconductor substrates such as of GaAs, InGaAs and thelike, SOI substrates and multilayer SOI substrates. Among them, thesilicon substrate is preferable. The semiconductor substrate may becombined with semiconductor elements such as transistors and capacitors;circuits thereof; wiring layers; device isolation films such as a LOCOSfilm, a trench device isolation film and an STI (shallow trenchisolation) film; and insulating films formed thereon.

[0033] In the present invention, a gate insulating film and a siliconfilm are formed in the step (a).

[0034] There is no particular limitation to material and thickness ofthe gate insulating film as long as they are generally applied tosemiconductor devices. For example, a single-layered or multi-layeredsilicon oxide film, silicon nitride film and the like are usable. Thethickness thereof may be about 2 to 7 nm, for example. The gateinsulating film may be formed by a known method, e.g., a thermaloxidization, a CVD method or the like.

[0035] The silicon film is preferably formed of silicon such aspolysilicon and amorphous silicon. Various kinds of method such as aknown method, a CVD method and an epitaxial growth may be used to formthe silicon film. The thickness of the silicon film is not particularlylimited but consideration should be given to inhibition of penetrationof impurities to the semiconductor substrate at ion implantation thereofand optional ion implantation to the semiconductor substrate through thesilicon film. Specifically, the thickness of the silicon film may beabout 40 to 100 nm if it is made of polysilicon or amorphous silicon.

[0036] Before the formation of the gate insulating film and the siliconfilm, an n-well may be formed only in a pMOS region of the semiconductorsubstrate. The n-well is provided by forming a protective film at leaston a surface of the pMOS region and implanting n-type impurities (e.g.,phosphorus, arsenic and antimony) into the semiconductor substratethrough the protective film. The protective film is not particularlylimited as long as its material and thickness allow protecting thesurface of the semiconductor substrate against the ion implantation. Forexample, an insulating film made of a single-layered or multi-layeredsilicon oxide film, silicon nitride film and the like is usable. Thethickness may be about 5 to 20 nm, for example. Conditions for the ionimplantation may suitably be adjusted depending on the depth of thewell, the kind of ion and the like. The ion implantation may preferablybe carried out in two or multiple steps at different doses and/ordifferent acceleration energies. For example, it may be two- ormultiple-step ion implantation set an implantation peak at a deeperregion and a shallower region than a device isolation region generallyformed in the semiconductor substrate. More specifically, the conditionsare optionally selected within a dose ranging about 1×10¹² to 5×10¹³ions/cm² and an acceleration energy ranging about 20 to 1000 keV.

[0037] In the step (b), n-type impurities are implanted in the siliconfilm in the nMOS region of the semiconductor substrate. The conditionsof the ion implantation are not particularly limited as long as theimpurities are uniformly diffused only within the silicon film whenannealed in a general manner in a later step, the obtained silicon filmappropriately functions as a gate electrode of the nMOS transistor andthe implanted impurities do not penetrate the silicon film and the gateinsulating film. Specifically, where the thickness of the silicon filmis within the above-mentioned range, the ion implantation is suitablycarried out in a dose of about 1×10¹⁵ to 5×10¹⁵ ions/cm² and anacceleration energy of about 5 to 30 keV (phosphorus) or about 10 to 50keV (arsenic).

[0038] The ion implantation is preferably performed with a mask havingan opening only above the nMOS region so that the n-type impurities areimplanted only in the silicon film in the nMOS region. The mask may be aresist mask formed by photolithography or a so-called hard mask made ofan insulting film (e.g., a silicon oxide film, a silicon nitride film orthe like).

[0039] Where the implantation of the n-type impurities in the step (b)is performed with the mask having the opening only above the nMOS regionas described above, it is preferred to form a p-well by implantingp-type impurities to the semiconductor substrate using the same maskbefore or after the n-type impurity implantation. The p-type impuritiesmay be boron, BF₂, indium or the like, among them boron is preferable.The p-well may preferably be formed by two- or multiple-step ionimplantation performed under the above-mentioned conditions.

[0040] Where the n-well has not been formed yet in the pMOS region ofthe semiconductor substrate before the formation of the gate insulatingfilm and the silicon film, the n-type impurities may be implanted in thestep (b) into the semiconductor substrate through the silicon film andthe gate insulating film using a mask having an opening only above thepMOS region to form the n-well as described above, as the step (b′).Further, the p-type impurities may be implanted to the silicon film inthe pMOS region with the mask having the opening only above the pMOSregion. It is preferred to perform both of the ion implantations intothe semiconductor substrate for forming the n-well and into the siliconfilm, but only one of them may be performed. The ion implantation may beperformed under the same conditions as those for the formation of thep-well and those for the n-type impurity implantation to the siliconfilm in the nMOS region except that different ion source is used.

[0041] In the step (b) and (b′), the ion implantation to the siliconfilm or the semiconductor substrate in the pMOS region and that to thesilicon film or the semiconductor substrate in the nMOS region may beperformed in any order. In consideration of the use of mask, the ionimplantations to the silicon film and the semiconductor substrate in thepMOS region are preferably carried out successively in this order oropposite order and the ion implantations to the silicon film and thesemiconductor substrate in the nMOS region are preferably carried outsuccessively in this order or opposite order.

[0042] In the step (b), where the ion implantation of the p-typeimpurities is not performed into the silicon film for pMOS transistor,the p-type impurities may be introduced into the silicon film byimplantation for forming source/drain regions or an LDD region describedlater.

[0043] In the step (c), a conductive film is formed on the silicon film.The conductive film may be a single layer or a multilayer made of, forexample, mono- or polyamorphous element semiconductors (e.g., silicon,germanium and the like); compound semiconductors (e.g., GaAs, InP, ZnSe,CsS and the like); metals such as gold, platinum, silver, copper,aluminum and the like; refractory metals such as titanium, tantalum,tungsten, cobalt and the like; silicide and polyside with refractorymetal; transparent conductive materials such as ITO, SnO₂, ZnO and thelike. Among them, a film of polysilicon, amorphous silicon, silicidewith refractory metal or metal is preferable. The thickness of theconductive film may be about 50 to 150 nm. The conductive film may beformed by various methods including a CVD method, a vapor deposition, anEB method, a sputtering and the like.

[0044] In the step (d) and (d′), the silicon film and the conductivefilm are patterned into a gate electrode. The patterning is performed byphotolithography and etching using a mask of a desired configuration.The mask may be a resist mask or a hard mask as described above.

[0045] In the present invention, an insulating film may be formed afterthe formation of the silicon film in the step (a) and before theformation of the conductive film in the step (c) such that the thicknessof the insulating film does not hinder electrical conduction between thesilicon film and the conductive film. The insulating film may be asingle-layered or multi-layered silicon oxide film, silicon nitride filmor the like, among which the silicon oxide film is preferable. Thethickness of the insulating film is not particularly limited as long asthe electrical conduction between the silicon film and the conductivefilm is ensured and it may be about 2 nm or less, for example. Theinsulating film may be formed at any time, e.g., immediately after theformation of the silicon film, before the formation of the p-well,before the optional formation of the n-well or immediately before theformation of the conductive film. Alternatively it may be formed withina period from immediately after the formation of the silicon film toimmediately before the formation of the conductive film. That is, theinsulating film may be formed intentionally at any time by a knownmethod such as a CVD method, a thermal oxidization or the like, or itmay be a so-called spontaneous oxide film automatically generated duringthe steps.

[0046] After a series of the formation steps described above,source/drain regions are formed in the nMOS and pMOS regions,respectively by performing ion implantation individually to one of thenMOS and pMOS regions while covering the other and using the obtainedlayered gate electrode as a mask. Ion sources and conditions for the ionimplantation may suitably be selected from those known in the art.

[0047] Alternatively, LDD regions may be formed in advance in the nMOSand pMOS regions, respectively by performing ion implantationindividually to one of the nMOS and pMOS regions while covering theother and using the obtained layered gate electrode as a mask, and thensidewall spacers are formed. Thereafter the source/drain regions may beformed by ion implantation with the sidewall spacers and the gateelectrode as a mask. Conditions of the ion implantation for forming theLDD regions and the method of forming the sidewall spacers may suitablybe selected from those known in the art.

[0048] Then, the semiconductor device of the present invention iscompleted by optionally combining the steps of forming interlayerinsulating films, forming contact holes and forming wiring layers aswell as washing the semiconductor substrate surface or the resultingsemiconductor substrate surface.

[0049] In the present invention, it is preferable to anneal thesemiconductor substrate obtained after the step (b), (c) or (d), orafter the step (b′), (c) or (d′). The annealing may be performed before,during or after any steps in any times as long as the ion implantationof the step (b) or (b′) has been performed. Preferably it is performedat least once immediately after the ion implantation for forming thesource/drain region. More preferably it is performed twice, i.e., onceimmediately after the ion implantation in the step (b) or (b′),immediately after the formation of the conductive film in the step (c)or immediately after the patterning to form the gate electrode in thestep (d) or (d′) and once again after the ion implantation for formingthe source/drain region. The annealing may be performed under conditionssuitably selected from those known in the art depending on the size ofthe obtained semiconductor device and the like. For example, it isperformed by lamp annealing at a temperature of about 1000 to 1100° C.for 5 to 20 seconds.

[0050] Hereinafter, embodiments of the process of manufacturing thesemiconductor device according to the present invention will be detailedwith reference to the drawings.

Embodiment 1

[0051] As shown in FIG. 1(a), device isolation regions 11 made of afield oxide film of 350 nm thick are formed in a semiconductor substrate10.

[0052] Then, a spontaneous oxide film generated on the semiconductorsubstrate 10 is removed to expose the surface of the semiconductorsubstrate 10. Then, a gate insulating film 12 made of a silicon oxidefilm of about 3.5 nm thick is formed on the semiconductor substrate anda polysilicon film 13 of about 100 nm thick are formed thereon as shownin FIG. 1(b).

[0053] As shown in FIG. 1(c), a resist mask 14 having an opening abovean nMOS region is formed by photolithography. With the resist mask 14,boron ions are implanted into the semiconductor substrate 10 through thepolysilicon film 13 and the gate insulating film 13 at an accelerationenergy of 300 keV, 180 keV, 95 keV and 50 keV and a dose of 1×10¹³ions/cm², 4×10¹² ions/cm², 2.5×10¹² ions/cm² and 3.5×10¹² ions/cm²,respectively to form a p-well 15 a. Again with the resist mask 14,phosphorus ions are implanted into the polysilicon film 13 at anacceleration energy of 10 keV and a dose of 2×10¹⁵ ions/cm² to form ann-type polysilicon film 13 a.

[0054] After removing the resist mask 14, a resist mask 16 having anopening above a pMOS region is formed as shown in FIG. 1(d) in the samemanner as the above. With the resist mask 16, phosphorus ions areimplanted into the semiconductor substrate 10 through the polysiliconfilm 13 and the gate insulating film 12 at an acceleration energy of 700keV, 380 keV, 200 keV and 80 keV and a dose of 1×10¹³ ions/cm², 8×10¹²ions/cm², 1.5×10¹² ions/cm² and 1.1×10¹² ions/cm², respectively to forman n-well 15 b. Again with the resist mask 16, boron ions are implantedinto the polysilicon film 13 at an acceleration energy of 5 keV and adose of 2×10¹⁵ ions/cm² to form a p-type polysilicon film 13 b.

[0055] After removing the resist mask 16, the resulting semiconductorsubstrate 10 is washed with hydrofluoric acid to remove a spontaneousoxide film and contaminants on the n- and p-type polysilicon films 13 aand 13 b. Then, an amorphous silicon film 17 of about 100 nm thick isformed on the n- and p-type polysilicon films 13 a and 13 b as shown inFIG. 1(e). Thereafter, lamp annealing is performed at about 1050° C. forabout 10 seconds to activate the thus implanted impurities.

[0056] Then, as shown in FIG. 1(f), the n- and p-type polysilicon films13 a and 13 b and the amorphous silicon film 17 are patterned into adesired configuration by photolithography and etching to form gateelectrodes.

[0057] Further, ion implantation is performed to the nMOS and pMOSregions to form LDD regions 19 a and 19 b, respectively, as shown inFIG. 1(g). The LDD region 19 a in the nMOS region is formed byimplanting arsenic ions at an acceleration energy of 15 keV and a doseof 3×10¹⁴ ions/cm². The LDD region 19 b in the pMOS region is formed byimplanting BF₂ ions at an acceleration energy of 10 keV and a dose of1×10¹⁴ ions/cm². At the ion implantation steps, impurities of thoseconductivity types are also implanted into a relatively shallow portionof the silicon film 17. Then, a silicon nitride film of about 100 nmthick is deposited on the entire surface of the thus obtainedsemiconductor substrate 10 and etched back to form sidewall spacers 18.

[0058] As shown in FIG. 1(h), ion implantation is performed to the nMOSand pMOS regions to form source/drain regions 20 a and 20 b,respectively. The source/drain region 20 a in the nMOS region is formedby implanting arsenic ions at an acceleration energy of 50 keV and adose of 2×10¹⁵ ions/cm². The source/drain region 20 b in the pMOS regionis formed by implanting BF₂ ions at an acceleration energy of 30 keV anda dose of 1.5×10¹⁵ ions/cm². At the ion implantation steps, impuritiesof those conductivity types are also implanted into a relatively deepportion of the silicon film 17.

[0059] Thereafter, lamp annealing is performed at about 1010° C. forabout 10 seconds to activate the thus implanted impurities. Through theannealing, the impurities implanted in the n- and p-type polysiliconfilms 13 a and 13 b and the amorphous silicon film 17 are diffusedwithin the gate electrodes. Since the impurities are sufficientlydiffused in the gate electrodes even if the annealing is performed atlow temperature for a short period of time, depletion of the gateelectrodes is inhibited, and thus a shallow junction is formed and thepenetration of boron ions are prevented.

[0060] Then, a cobalt film is formed on the obtained semiconductorsubstrate 10 and thermally treated to form a cobalt silicide film 21 onthe gate electrodes and the source/drain regions 20 a and 20 b as shownin FIG. 1(i). Thereafter, an interlayer insulating film 22 and contactholes are formed, and then contact plugs 23 and a wiring layer 24 areformed in a wiring step. Thus, a dual gate CMOS transistor is completed.

Embodiment 2

[0061] As shown in FIG. 2(a), device isolation regions 31 are formed ina semiconductor substrate 30 in the same manner as in Embodiment 1.

[0062] Then, a protective film 32 against the implantation made of asilicon oxide film is formed on the entire surface of the semiconductorsubstrate 30 as shown in FIG. 2(b). On the thus obtained semiconductorsubstrate 30 a resist mask 33 having an opening only above a pMOS regionis formed. With the resist mask 33, phosphorus ions are implanted intothe semiconductor substrate 30 at an acceleration energy of 600 keV, 300keV, 150 keV and 40 keV and a dose of 1×10¹³ ions/cm², 8×10¹² ions/cm²,1.5×10¹² ions/cm² and 1.1×10¹³ ions/cm², respectively to form an n-well34 b.

[0063] After removing the resist mask 33, the protective film 32 isremoved to expose the surface of the semiconductor substrate 30 and agate insulating film 35 made of a silicon oxide film of about 3.5 nmthick is formed thereon. Further, a polysilicon film 36 of about 50 nmthick is formed thereon as shown in FIG. 2(c).

[0064] Then as shown in FIG. 2(d), a resist mask 37 having an openingonly above an nMOS region is formed as described above. With the resistmask 37, boron ions are implanted into the semiconductor substrate 30through the polysilicon film 36 and the gate insulating film 35 at anacceleration energy of 280 keV, 160 keV, 80 keV and 35 keV and a dose of1×10¹³ ions/cm², 4×10¹² ions/cm², 2.5×10¹² ions/cm² and 3×10¹² ions/cm²,respectively to form a p-well 34 a. Again with the resist mask 37,phosphorus ions are implanted into the polysilicon film 36 at anacceleration energy of 10 keV and a dose of 2×10¹⁵ ions/cm² to form ann-type polysilicon film 36 a.

[0065] After removing the resist mask 37, the thus obtainedsemiconductor substrate 30 is washed with hydrofluoric acid in the samemanner as in Embodiment 1. Then, an amorphous silicon film 38 of about100 nm thick is formed on the polysilicon film 36 and the n-typepolysilicon film 36 a as shown in FIG. 2(e).

[0066] Further, as shown in FIG. 2(f), the polysilicon film 36, then-type polysilicon film 36 a and the amorphous silicon film 38 arepatterned into a desired configuration by photolithography and etchingto form gate electrodes.

[0067] Then, ion implantation is performed to the nMOS and pMOS regionsto form LDD regions 40 a and 40 b, respectively as shown in FIG. 2(g) inthe same manner as in Embodiment 1. Thereafter, sidewall spacers 39 areformed onto the gate electrodes.

[0068] Then, ion implantation is further performed to the nMOS and pMOSregions to form source/drain regions 41 a and 41 b, respectively asshown in FIG. 2(h). The source/drain region 41 a in the nMOS region isformed by implanting arsenic ions at an acceleration energy of 50 keVand a dose of 3×10¹⁵ ions/cm². The source/drain region 41 b in the pMOSregion is formed by implanting BF₂ ions at an acceleration energy of 30keV and a dose of 2×10¹⁵ ions/cm².

[0069] Thereafter, lamp annealing is performed at about 1020° C. forabout 10 seconds to activate the thus implanted impurities. As a resultof the annealing, the impurities implanted in the n-type polysiliconfilm 36 a and the amorphous silicon film 38 are diffused within the gateelectrode in the nMOS region, which prevents depletion of the gateelectrode. Further, boron ions implanted as impurities in the amorphoussilicon film 38 in the pMOS region are sufficiently distributed withinthe gate electrode even if the annealing is performed at low temperaturefor a short period, which prevents depletion of the gate electrode.Thus, a shallow junction is obtained and penetration of boron ions areprevented.

[0070] Then, a cobalt silicide film 42, an interlayer insulating film43, contact holes, contact plugs 44 and a wiring layer 45 are formed inthe same manner as in Embodiment 1 to complete a dual gate CMOStransistor as shown in FIG. 2(i).

[0071] According to the present invention, particularly in the gateelectrode in the nMOS region where depletion has easily been happened,sufficient impurity concentration is maintained entirely in the gateelectrode and the impurities of a sufficient amount are efficientlyintroduced into an interface between the gate electrode and the gateinsulating film. Thus, the depletion of the gate electrode in the nMOSregion is prevented while inhibiting short channel effect and reducingOFF current without multiplying particular manufacturing steps andprolongation of the steps.

[0072] Further, penetration of the p-type impurities, in particularboron ions, through the gate insulating film due to high diffusivenessof boron is prevented in the pMOS transistor. Accordingly, aminiaturized dual gate CMOS transistor of high performance and highreliability is manufactured.

[0073] That is, according to a series of steps of the present invention,impurities can be implanted in advance in a lower portion of the gateelectrode. Therefore the impurities are effectively introduced at asufficient concentration into the neighborhood of an interface betweenthe gate insulating film and the gate electrode without being affectedby the conditions of ion implantation for forming the source/drainregion and annealing performed later, as well as material of the gateelectrode. Thus, the depletion of the gate electrode is advantageouslyinhibited. Further, since the impurities can be diffused into a requiredportion by a thermal treatment for a relatively short period, asource/drain region of shallow junction is easily formed and thepenetration of boron ions through the gate insulating film in the pMOStransistor is prevented. Therefore, the threshold value of thetransistor can be controlled.

[0074] In the step (b), where the n-type impurities are implanted to thesemiconductor substrate in the nMOS region with a mask having an openingonly above the nMOS region before or after ion implantation to thesilicon film, the mask is used for both of the ion implantation steps sothat multiplication of masking steps is prevented. Further, another ionimplantation for forming the well is performed after the gate insulatingfilm is formed, which inhibits unnecessary thermal diffusion of theimpurities implanted for forming the well. For example, decrease orincrease in the impurity concentration at an interface between the welland the device isolation region generally formed in the semiconductorsubstrate are inhibited, which improves field properties.

[0075] Further, in the step (b), where the n-type impurities areimplanted to the semiconductor substrate with a mask having an openingonly above the pMOS region in two or multiple steps at two or moredifferent acceleration energies and/or two or more different doses, awell of optional depth is easily formed with uniform impurityconcentration and the impurity concentration of a deeper portion of thewell is easily increased. This is advantageous in preventing latch-up.

[0076] Still further in the step (b), where the p-type impurities areimplanted into the silicon film in the pMOS region of the semiconductorsubstrate before or after the n-type impurity implantation to thesemiconductor substrate, a mask for the n-type impurity implantation isused also for the p-type impurity implantation. Therefore, sufficientimpurity concentration is ensured entirely within the gate electrode inthe pMOS region and in an interface between the gate electrode and thegate insulating film. Thus, depletion of the gate electrode in the nMOSregion is prevented while inhibiting short channel effect and reducingOFF current without multiplying and lengthening particular manufacturingsteps.

[0077] Where the conductive film is made of a silicide film or a metalfilm in the step (c), resistance at the gate electrode is easilyreduced, which is advantageous to next-generation techniques.

[0078] Further, where an insulating film is formed after the formationof the silicon film in the step (a) and before the formation of theconductive film in the step (c) to have a thickness which does nothinder electrical conduction between the silicon film and the conductivefilm, action of fluorine which badly promotes the penetration of boronions through the gate insulating film is inhibited, which effectivelyprevents the penetration of boron ions through the gate insulating filmin the pMOS region.

[0079] Where the semiconductor substrate is subjected to annealing afterthe step (b), (c) or (d), the impurities implanted in the gate electrodeare sufficiently diffused so that the depletion of the gate electrode isadvantageously prevented.

What is claimed is:
 1. A process of manufacturing a semiconductor devicehaving a dual gate CMOS transistor in which an nMOS transistor in thedual gate CMOS transistor is formed by the steps of: (a) forming a gateinsulating film and a silicon film on a semiconductor substrate; (b)implanting n-type impurities into the silicon film in an nMOS region ofthe semiconductor substrate; (c) forming a conductive film on thesilicon film; and (d) patterning the silicon film and the conductivefilm into a gate electrode.
 2. A process according to claim 1, whereinin the step (b) the n-type impurities are implanted into the siliconfilm with a mask having an opening only above the nMOS region, andp-type impurities are further implanted into the semiconductor substratethrough the gate insulating film and the silicon film using the samemask before or after the n-type impurity implantation.
 3. A processaccording to claim 2, wherein the ion implantation into thesemiconductor substrate is performed at two or more kinds ofacceleration energies and/or two or more kinds of doses.
 4. A processaccording to claim 1, wherein the conductive film formed in the step (c)is made of a silicide film or a metal film.
 5. A process according toclaim 1, wherein an insulating film having a thickness which does notprevent electrical conduction between the silicon film and theconductive film is formed after the formation of the silicon film in thestep (a) and before the formation of the conductive film in the step(c).
 6. A process according to claim 1, wherein the obtainedsemiconductor substrate is annealed after the step (b), (c) or (d).
 7. Aprocess according to claim 1, wherein source/drain regions are formed byan ion implantation after the step (d).
 8. A process of manufacturing asemiconductor device having a dual gate CMOS transistor comprising thesteps of: (a) forming a gate insulating film and a silicon film on asemiconductor substrate; (b′) implanting n-type impurities into thesilicon film in an nMOS region and p-type impurities into the siliconfilm in an pMOS region of the semiconductor substrate; (c) forming aconductive film on the silicon film; and (d′) patterning the siliconfilm and the conductive film into gate electrodes for the nMOS and pMOStransistor.
 9. A process according to claim 8, wherein in the step (b′)the n-type impurities are implanted into the silicon film with a maskhaving an opening only above the nMOS region, and p-type impurities arefurther implanted into the semiconductor substrate through the gateinsulating film and the silicon film using the same mask before or afterthe n-type impurity implantation.
 10. A process according to claim 8,wherein in the step (b′) the p-type impurities are implanted into thesilicon film with a mask having an opening only above the pMOS region,and n-type impurities are further implanted into the semiconductorsubstrate through the gate insulating film and the silicon film usingthe same mask before or after the p-type impurity implantation.
 11. Aprocess according to claim 9 or 10, wherein the ion implantation intothe semiconductor substrate is performed at two or more kinds ofacceleration energies and/or two or more kinds of doses.
 12. A processaccording to claim 8, wherein the obtained semiconductor substrate isannealed after the step (b′), (c) or (d′).
 13. A process according toclaim 8, wherein source/drain regions are formed by an ion implantationafter the step (d′).